first file in sim and rtl folder is mux and inside the other folder is d-flip flop

2X1_mux_verifcation_using_system_verilog

2x1 mux is verification is done using system verilog. For verification of mux all component are designed and simulated .

rtl design -verilog

testbench -systemverilog,

tool-edaplayground and questasim

simulation output

waveform

Dflip -flop

simulation