24-12_DIGITAL_CLOCK_DESIGN_USING_VERILOG

DESIGN DIGITAL CLOCK FOR 24/12 HOURS, USING TWO BLOCKS COUNTER AND BCD TOSEVEN SEGMENT. ALL CODE WRITTEN IN VERILOG.

24-12_DIGITAL_CLOCK_DESIGN_USING_VERILOG

designing a rtl verilog code for 24 hours digital clock. the output is represent using 6- seven segment . 6- seven segment used for sec_l,sem_m,min_l, min_m,hr_l,hr_m. the design have two inputs clk and rst and 6 outputs which represents using 6-seven segment . top module design using counter and bcd to seven segment block design instantiation.

BLOCK DESGIN- 1) TOP MODULE

2) COUNTER

3)BCD_SEVEN_SEGMENT

WAVEFORM